Latch circuits are extensively used within logic circuitry (e.g., microprocessor design) to temporarily store data until a succeeding circuit needs the data. One such type of latch is an edge triggered latch commonly used in the industry. "Edge triggered latch" is really a misnomer, since the latch is actually responding to some type of narrow pulse. An ideal pulse is as narrow as possible, but can still guarantee that the pulse is wide enough to cause the latch to evaluate. Prior art solutions have generated pulses which are 3-5 inversions wide. As the pulse becomes wider though, an early mode problem develops. That is, if the latch is transparent for greater than the amount of delay through the latch, then it is possible for a race condition to exist.
For the prior art schemes with 3-5 inversions, the designer would be required to place circuitry between successive latches to guarantee that no data could flush through two series latches while they were both transparent. This is sometimes referred to as "padding" the cycle with delay circuits, such as shown in circuit 200 in FIG. 2. In circuit 200, the transparency window is the width of the delays through inverters 201, 202, and 203. NFETs 204 and 205 complete the construction of the one-shot pulse generator caused by the rising edge of the clock signal (CLK).
The problem with circuit 200 is that the delay must be carefully designed to permit a proper evaluation of the incoming data but yet eliminate the early mode problem. It can be easily appreciated that such a design is difficult and time consuming, and the resultant design may fail due to variations in operating parameters, such as clock skew. As a result, there is a need in the art for an improved edge triggered latch design.